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School of Electronic Engineering and Computer Science

Digital Circuit Design

Module code: ECS412U

Credits: 15.0
Semester: SEM1
Timetable:

    Tutorial
  • Semester 1: Tuesday 5 pm - 6 pm
    Lecture
  • Semester 1: Tuesday 9 am - 11 am
    Lab
  • Semester 1: Weeks 4, 6, 8, 11: Friday 2 pm - 5 pm
  • Semester 1: Weeks 5, 7, 9, 11: Friday 11 am - 2 pm

Contact: Dr Paula Freire Fonseca
Overlap: None
Prerequisite: None

The module covers: Number Systems and Codes; Boolean Algebra and Basic Logic Functions; MAP minimisation; Combinational Logic; Synchronous Sequential Logic; VHDL

Connected course(s): UDF DATA
Assessment: 75.0% Examination, 25.0% Coursework
Level: 4

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