Somayyeh Timarchi

Profile

SOMAYYEH TIMARCHI received her B.Sc. in computer engineering from Shahid Beheshti University (SBU). She received her M.Sc. and Ph.D. in computer system architecture from Sharif University of Technology (SUT) and Shahid Beheshti University, in 2005 and 2010, respectively. She also performed studies on computer arithmetic as a postdoc researcher at the Computer Engineering Laboratory, Delft University of Technology (TUDelft). Then, she joined the Department of Electrical Engineering at Shahid Beheshti University as an assistant professor and was promoted to associate professor. Now, she is a lecturer in the School of Electronic Engineering and Computer Science at Queen Mary University of London (QMUL). She has authored or co-authored more than 50 publications in journals and conference proceedings. Her research interests include Computer arithmetic, Approximate computing, Neuromorphic computing, ASIC/FPGA design for signal processing, cryptography, and IoT applications, Residue and Redundant Number Systems, and Low-power Digital Design.

Undergraduate Teaching

ECS502U - Microprocessor Systems Design (Undergraduate)

This module examines the structure, applications and programming of microcontrollers and similar devices. There will be practical work on using the devices as part of the module. Aims:

* To impart an understanding of the architectures of microcontrollers microprocessors, and PIC devices.

* To impart an understanding of the design issues in using microcontrollers and similar devices.

* To enable students to make an informed choice of microcontrollers or similar device for a particular application.

* To enable students to use microcontroller devices in electronic circuits.

Fellow of the Higher Education Academy (FHEA)

Research

Research Interests:

My research interests lie in the field of high-speed, low-power digital architecture, with a focus on enhancing computer arithmetic units. We employ low-power design techniques and optimized arithmetic circuits to develop efficient digital systems for applications in IoT, image and signal processing, neuromorphic computing, cryptography, and biomedical engineering. In recent years, our work has concentrated on approximate computing to improve the hardware performance of neural networks (NNs), such as Spiking Neural Networks (SNNs) and Convolutional Neural Networks (CNNs), while maintaining high levels of precision. For low-power arithmetic design, we focus on arithmetic units suitable for energy-efficient chips. This includes CORDIC-based spiking neural networks, redundant CORDIC-based FFT and DCT architectures, and low-power DCT-based image compressor for wireless capsule endoscopy that can be applied to implantable and wearable biomedical systems.

Publications

1. Sayyadi, A. Amirany, M.H. Moaiyeri, S. Timarchi, “Balancing Precision and Efficiency: An Approximate Multiplier with Built-in Error Compensation for Error Resilient Applications”, The Journal of Supercomputing, 2025.
2. Sayyadi, S. Timarchi, A. Sheikh-Akbari "Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors", IEEE Transactions on Circuits and Systems I: Regular Papers, 2023.
3. M. Sadeghi, S. Timarchi and M. Fazlali, "High-Performance Memory Allocation on FPGA With Reduced Internal Fragmentation," IEEE Access, vol. 11, pp. 66672-66681, 2023.
4. Raouf, S. Timarchi, “Non-Volatile and High-Performance Cascadable Spintronic Full-Adder with no Sensitivity to Input Scheduling”, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 70, Issue: 6, pp. 2236 – 2240, June 2023.
5. Timarchi, “Teaching Redundant Residue Number System for Electronics and Computer Students”, International Journal of Mathematical Education in Science and Technology, Volume 54, Issue 10, pp: 2027-2045, 2023.
6. A. Birgani, S. Timarchi, A. Khalid, “Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography”, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022.
7. A. Birgani, S. Timarchi, A. Khalid, “Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization”, Microprocessors and Microsystems 93, 104588, 2022.
8. M Raouf, Timarchi, “Reducing the Effect of Carry Propagation on Spintronic Adders”, Spin 12 (1), 2150032-7, 2022.
9. A.H. Ejtahed, S. Timarchi, “Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor”, Circuits, Systems, and Signal Processing 41 (5), 2699-2718, 2022.
10. Torabi, S. Timarchi, “Sign Detection and Signed Integer Comparison for the 3-Moduli Set {2^ n±1, 2^(n+ k)}, Computer Science, vol. 22, issue 3, 2021.
11. A Shabani, M Sabri, B Khabbazan, Timarchi, “Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 68, Issue: 3, Mar. 2020, pp. 1259-1268.
12. Talebi, S. Timarchi, “Improved Distributed Particle Filter Architecture with Novel Resampling Algorithm for Signal Tracking”, International Journal of Engineering, Vol. 33, Issue: 12, Dec. 2020, pp. 2482-2488.
13. Mahdavi, S. Timarchi, “Improving Architectures of Binary Signed-Digit CORDIC with Generic/Specific Initial Angles”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, Issue: 10, Oct. 2020, pp. 2297-2304.
14. Mahdavi, S. Timarchi, “Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, Issue: 10, Oct. 2019.
15. Shabani, S. Timarchi, H. Mahdavi, "Power and Area Efficient CORDIC-Based DCT Using Direct Realization of Decomposed Matrix", Microelectronics Journal, Vol. 91, Sep. 2019, pp.11-21.
16. Armand, S. Timarchi, "Efficient Error Detection and Correction Method for 1-out-of-3 Binary Signed Digit Adders", the International Journal of Electronics, Vol. 106, Issue 9, 18 Apr. 2019, pp. 1427-1440.
17. Timarchi, N. Akbarzadeh, "Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2^n-1 Adder and Multiplier ", Circuits, Systems, and Signal Processing, Vol. 38, Issue 5, May 2019, pp 2138–2164.
18. Armand, S. Timarchi, “Optimized parity-based error detection and correction methods for residue number system”, Journal of Circuits, Systems, and Computers (JCSC), Vol. 28, No. 1, 2019.
19. Naseri, S. Timarchi, “Low Power and Fast Full Adder by Exploring New XOR and XNOR Gates”, IEEE Transactions on Very Large Scale Integrated (TVLSI) Systems, Vol. 26, Issue 8, 16 Apr. 2018, pp. 1481-1493.
20. Akbarzadeh, S. Timarchi, “Modulo 2ⁿ+1 Multiplication and Multiply-Accumulate Units for Digital Signal Processor”, Journal of Signal and Data Processing (JSDP), Vol. 15, Issue 1, 2018, pp. 127-138.
21. Shabani, S. Timarchi, “Low-power DCT-based compressor for wireless capsule endoscopy”, Signal Processing: Image Communication, Vol. 59, Nov. 2017, pp. 83-95.
22. Abbasi Alaie, S. Timarchi, "Efficient modulo 2n +1 multiplier", Int. J. Computer Aided Engineering and Technology, vol.8, no.3, pp. 260-276, 2016.
23. Moghaddam, S. Timarchi, M.H. Moaiyeri, M. Eshghi,"An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques", Circuits, Systems, and Signal Processing, Vol. 35, Issue 5, 2016, pp 1437–1455.
24. Fazlali, H. Valikhani, S. Timarchi, H. Tabatabaee, "Fast Architecture for Decimal Digit Multiplication" Microprocessors and Microsystems, Elsevier, Vol. 39, Issues 4-5, June–July 2015, pp. 296–301.
25. Timarchi, M. Fazlali "Generalized Fault-Tolerant Stored-Unibit-Transfer RNS Multiplier for Moduli Set {2ⁿ-1, 2ⁿ, 2ⁿ+1}", IET Computers and Digital Techniques, vol. 6, issue 5, Sep. 2012, pp. 269-276.
26. Saremi, S. Timarchi, "Efficient Modular Binary Signed-Digit Multiplier for the moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1}", the CSI Journal of Computer Science and Engineering, Vol. 9, No. 2 & 4(b), pp. 52-62, 2011.
27. Sabbagh, K. Navi, Ch. Dadkhah, O. Kavehei, and S. Timarchi, "Efficient Reverse Converter Designs for the New 4-Moduli Sets {2ⁿ–1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹–1} and {2ⁿ–1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1} Based on New CRTs", IEEE Transactions on Circuit and Systems I, vol.57, no.4, April 2010.
28. Timarchi, K. Navi, "Arithmetic Circuits of Redundant SUT-RNS", IEEE Transactions on Instrumentation and Measurement, vol.58, no.9, Sep. 2009, pp.2959-2968.
29. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, "A Novel Low-Power Full-Adder Cell for Low Voltage", Integration, the VLSI Journal, vol. 42, Issue 4, Sep. 2009, pp. 457-467.
30. Timarchi, K. Navi, "A New Algorithm for Determining All Possible Symmetric Hybrid Redundant Numbers," IEICE Electronics Express, Vol.6, No.1, pp.8-13, January 10, 2009.
31. Timarchi, O. Kavehei, K. Navi, "Low Power Modulo 2ⁿ+1 Adder Based on Carry Save Diminished-One Number System," American Journal of Applied Sciences 5 (4), pp.312-319, 2008.
32. Timarchi, K. Navi, "Improved Modulo 2ⁿ+1 Adder Design," International Journal of Computer and Information Science and Engineering, Vol. 2, No.3, pp. 158-165, Summer 2008.